1. Field of the Invention
The invention relates to methods and systems for design, layout, and routing of integrated circuits using alternating aperture phase shift masks.
2. Description of Related Art
The features of small integrated circuit semiconductor devices, such as microprocessors, are usually defined by using lithographic techniques on a semiconductor wafer. A typical lithographic mask for semiconductor photolithography processes is a sheet of quartz onto which a layer of chrome or another opaque material is deposited in patterns that define the shapes which are to be reproduced lithographically on the semiconductor wafer.
As better technologies have allowed the features of a semiconductor device to become smaller and smaller, feature size has begun to approach the theoretical minimum size that can be faithfully reproduced by conventional lithographic techniques. Therefore, as feature sizes have become smaller and smaller, engineers have turned to a number of Resolution Enhancement Techniques (RET) that improve the resolution of the conventional processes.
One RET is a technique known as Alternating Aperture Phase Shift Masks (AltPSM). In general, AltPSM makes use of the constructive and destructive interference of light to sharpen the edges and increase the resolution of lithographically reproduced features. Specifically, some portions of AltPSM masks are etched so as to be thinner, or have additional layers of transparent material deposited on them so as to be thicker. Changing the depth of material through which light passes during lithography alters the phase of the light. By selecting and controlling the depth (i.e., thickness) of the mask, an AltPSM mask can have areas in which the light passing through the mask is 180.degree. out of phase with respect to the other areas of the same mask. When light that is 180.degree. out of phase meets at the wafer, either constructive interference or destructive interference may occur, and the interfering light defines the pattern to which the (usually photoresist-covered) wafer is actually exposed. Typically, light of a particular wavelength (e.g., currently 193 nanometers (nm)) is used in semiconductor lithography. Resolution Enhancement Techniques such as AltPSM may be used to print features smaller than the wavelength of the light.
When using AltPSM techniques in integrated circuit design and layout, features that approach the minimum size may be defined, at least in part, by shapes having the phases necessary to cause interference and create the desired feature. Two primary types of AltPSM are in use: bright field and dark field. The two techniques are complements of one another. In bright field AltPSM, phase shifting shapes are added to the layout to sharpen the focus of the design features. In dark field AltPSM, phases are added to the design features themselves to define and sharpen the spaces between the features.
For example, FIG. 1 is a depiction of an exemplary phase-correct bright field AltPSM layout 10. The actual shape of the feature 12 is flanked on each side by a phase shape 14, 16. The two phase shapes 14, 16 have phases that are 180.degree. out of phase, so that interference of light will define the desired feature 12.
FIG. 2 is a depiction of an exemplary phase-correct dark field AltPSM layout 20. In the dark field layout 20, three wires 22, 24, 26 are given particular phases; the uppermost and lowermost phase wires 22, 26 in FIG. 2 have the same phase, and the center wire 24 has a phase 180.degree. out of phase with the other two wires 22, 26; therefore interference between the center wire 24 and the top and bottom wires 22, 26 will define and sharpen the spaces between the wires.
Typically, bright field AltPSM is used for polysilicon layers and dark field AltPSM is used for metal layers (e.g., wiring layers). The overall process of determining the location and phase of AltPSM phase shapes is sometimes referred to as “phase coloring,” particularly in the case of dark field AltPSM, in which phases are added to existing shapes or features. AltPSM layouts and routings may be determined for an entire integrated circuit together, or for smaller individual portions of the circuit, for example, between a certain group of standard or “book” elements in one portion of the integrated circuit.